High-speed digital circuits are evolving towards ultra-high speeds such as 56Gbps PAM4 and 112Gbps NRZ. Electromagnetic compatibility (EMC) issues have risen from an auxiliary design stage to a core factor determining the success or failure of a product. The traditional serial mode of "design - test - rectification" is difficult to meet the development requirements of high-end products such as AI servers and 800G optical modules due to its long cycle and high cost. This paper proposes a full-process closed-loop control method based on "schematic diagram -PCB- test verification". Through technological innovations such as electromagnetic simulation in advance, signal-power collaborative optimization, and dynamic impedance compensation, it realizes a paradigm shift from passive rectification to active prevention of EMC problems.
I. Electromagnetic Risk Prediction and Control in the Schematic Stage
The root cause of the EMC problem in high-speed digital circuits lies in the coupling effect of signal integrity (SI) and power integrity (PI). The core contradiction is reflected in the conflict between signal edge rate and dielectric loss, as well as the superposition of power fluctuation and ground bullet noise. In the schematic design stage, a "digital twin" model needs to be constructed through electromagnetic simulation pre-technology: the ADS software is used to establish channel simulation including the IBIS model. While analyzing the quality of the signal eye diagram in the time domain, the frequency-domain impedance characteristics are obtained through S-parameter extraction. After adopting this technology, the 112G SerDes channel developed by a certain enterprise identified the impedance mutation point caused by the 0.8mm trace length in advance, compressing the crosstalk noise from -30dB to -45dB and avoiding subsequent PCB rework.
The design of power supply networks needs to break away from the traditional single goal of "low impedance" and shift to a "dynamic impedance matching" strategy. Through the SI/PI collaborative simulation platform, the frequency-domain impedance requirements for power integrity (such as DC-100 MHZ impedance <10mΩ) and the time-domain overcharge control for signal integrity (such as 10%-90% rise time <50ps) are jointly optimized. After a certain AI acceleration card project adopted this solution, under a 200A current load, the power supply ripple was reduced from 120mV to 45mV, and the timing margin of key signals was increased from 150ps to 300ps.
Ii. Electromagnetic Coupling Suppression Technology for PCB Layout and Routing
PCB stacking design is a strategic high ground in EMC control. Its core lies in achieving a balance among signal loss, power efficiency and heat dissipation performance through the selection of dielectric materials and the optimization of stacking structure. In the design of 800G optical modules, a symmetrical stacking structure of "signal layer - power layer - signal layer - ground layer" is adopted, with 0.1mm thick RO4350B low-loss dielectric (Df=0.0037@10GHz) embedded in the middle. Reduce the insertion loss of the 112G PAM4 signal from 4.5dB/inch to 2.8dB/inch. Meanwhile, a 0.05mm thick bonding sheet is inserted between the power layer and the ground layer to increase the interlayer capacitance density to 0.5nF/cm², effectively suppressing high-frequency switching noise.
The routing of key signals must follow the dual constraints of the "3W Rule" and "differential pair equal-length control". For PCIe 5.0 signals, the single-ended trace spacing should be ≥3 times the line width (approximately 0.45mm), and the differential internal length difference should be controlled within ±5mil. After the DPU chip developed by a certain enterprise adopted this specification, the near-end crosstalk (NEXT) was optimized from -25dB to -40dB, and the far-end crosstalk (FEXT) was reduced from -20dB to -35dB. In addition, by setting up "ground protection" traces below the critical signals, the coupled noise can be further reduced by 10-15dB.
Iii. Synergistic Optimization of Power Supply Integrity and Ground Plane Segmentation
The core challenge of power integrity design lies in simultaneously meeting the dual requirements of low impedance (DC-100 MHZ) and high-frequency decoupling (100 MHZ -10GHz). Traditional multilayer ceramic capacitors (MLCCS) are difficult to cover the entire frequency band due to the limitation of their self-resonant frequencies. The innovative solution adopts a hybrid decoupling strategy of "tantalum capacitor +MLCC+ embedded capacitor" : A 100μF tantalum capacitor is placed at the power supply inlet to provide low-frequency energy storage. A 0402 package MLCC(10nF/100nF) is arranged near the chip pins to suppress medium-frequency noise. Meanwhile, a 0.1μF/cm² distributed capacitor layer (composed of the power supply layer and the ground layer) is embedded in the inner layer of the PCB to absorb high-frequency switching energy. After the CPU power supply design of a certain server adopted this scheme, when the current suddenly changed by 100A, the power supply voltage fluctuation was reduced from 80mV to 25mV, meeting the strict power supply requirements of Intel Xeon Scalable processors.
Ground plane segmentation is a "double-edged sword" in EMC design. Reasonable segmentation can isolate sensitive signals, but improper operation can cause ground bomb noise. The innovative method adopts a hybrid architecture of "star grounding + local isolation" : a 0.2mm wide isolation slot is set at the junction of the digital circuit and the analog circuit, and single-point connection is achieved through magnetic beads or 0Ω resistors. After a certain medical imaging device adopted this technology, the common-mode noise of the analog signal was reduced from 50mV to 5mV, and the image signal-to-noise ratio was improved by 12dB.
Iv. EMC Testing Verification and Closed-loop Correction Mechanism
EMC testing needs to break through the limitations of traditional anechoic chambers and build a hybrid verification system of "near-field scanning + far-field radiation". During the R&D stage, the Keysight N9918A handheld spectrum analyzer was used for near-field scanning to quickly locate noise hotspots on the PCB (such as DC-DC converters and clock generators). The 5G small base station project developed by a certain enterprise detected the second harmonic leakage problem of the clock signal in advance through this technology. By adding a ground pad below the crystal oscillator, the radiated noise was reduced from -80 DBM to -100 DBM.
Far-field radiation testing needs to be combined with 3D electromagnetic simulation for reverse traceability. When the test found that the 1.2GHz frequency point exceeded the standard, an accurate model of the PCB was established through the HFSS software, and the circular current path of the power layer was located in combination with the near-field scanning data. The correction plan includes adding four 0402 packaged beads on the annular path to compress the 1.2GHz radiated noise from -70 DBM to -95 DBM, meeting the CISPR 32 Class B standard.
V. Full-process Closed-loop Control and Digital Empowerment
The core of the full-process closed-loop control lies in establishing a data chain of "design - simulation - testing - correction". By developing the EMC Design Rule Checking (DRC) tool, requirements such as impedance control, spacing constraints, and decoupling capacitor layout are transformed into automated scripts, intercepting over 80% of potential issues in real time during the PCB design stage. The digital EMC platform built by a certain enterprise integrates toolchains such as ADS, HFSS, and SIwave, achieving seamless transmission of electromagnetic characteristics from schematic diagrams to PCBS. This has shortened the R&D cycle from six months to three months and increased the first-time pass rate from 65% to 92%.
Driven by AI and big data technologies, EMC design is evolving towards intelligence. The neural network model trained by a certain enterprise can predict the radiation hotspots of PCBS based on historical project data, with an accuracy rate of 85%. By embedding this model into EDA tools, designers can obtain optimization suggestions during the layout stage and solve EMC problems in their infancy.
The full-process closed-loop control from schematic diagrams to PCBS marks the leap of EMC design from experience-driven to data-driven. Through technological innovations such as electromagnetic simulation in advance, signal-power collaborative optimization, and dynamic impedance compensation, combined with digital toolchains and AI empowerment, enterprises can build an EMC defense system of "prevention - control - correction". Driven by emerging fields such as 6G communication, smart vehicles, and industrial Internet, this methodology will become the core competitiveness of high-speed digital circuit design and provide fundamental guarantees for the electromagnetic compatibility of the next generation of electronic products.